Ph.D. 1981, University of Illinois at Urbana-Champaign, Computer
Science
M.S. 1977, Univerity of Massachusetts at Amherst, Computer
Engineering
B.S. 1972, National Taiwan University, Electrical Engineering
.
Professional Background
1994-present, Professor, Department of Computer Science and
Engineering, University of Minnesota at Twin-Cities
2001-2005, William Norris Land-Grand Chair Professor,
Department of Computer Science and Engineering, University of Minnesota
at Twin-Cities
2000-2005, Head, Department of Computer Science and
Engineering, University of Minnesota at Twin-Cities
1992-1994, Associate Director, Center for Supercomputing Research
and Development, University of Illinois at Urbana-Champaign
1991-1992, Director, Microelectronic Systems Architecture
Program, Division of Microelectronic Information Processing Systems,
National Science Foundation.
1991-1994, Associate Professor, Department of Electrical and
Computer Engineering, and Department of Computer Science, University of
Illinois at Urbana-Champaign
1987-1991, Assistant Professor, Department of Electrical and
Computer Engineering, and Department of Computer Science, University of
Illinois at Urbana-Champaign
Editorship
2002-2005, Editor-in-Chief, IEEE Transactions on Parallel and
Distributed Systems
1993-1997, Associate Editor, IEEE Transactions on Parallel and
Distributed Systems
1989-1995, Subject Area Editor, Journal of Parallel and
Distributed Computing, Academic Press, Inc.
2000, Guest Editor of a special issue on Parallel and Distributed Systems,
Journal of Information Science and Engineering Academia Sinica
1999, Guest Editor of a special issue on Compilers and Languages for Parallel and
Distributed Computers, IEEE Transactions on Parallel and
Distributed Systems
1995, Guest Editor of a special issue on Memory Organization in Parallel Computers,
Journal of Parallel and Distributed Computing
1991, Guest Editor of a special issue on Parallel Languages and Compiler, IEEE
Transactions on Parallel and Distributed System
1991, Guest Editor of a special issue on Shared-Memory Multiprocessors,
Journal of Parallel and Distributed Computing
Professional Activities
IEEE Fellow
General Chair, International Conference on Parallel
and Distributed Systems (ICPADS), Minneapolis, MA (2006)
Program Co-Chair, 9th Asian-Pacific Computer Systems Architecture
Conference (ACSAC), Beijing, China (2004)
Program Co-Chair, International Conference on High Performance
Computer Architecture (HPCA), Boston, MA (2002)
Program Vice-Chair, International Parallel and Distributed
Processing Symposium (IPDPS), San Francisco, CA (2001)
Program Vice-Chair, International Conference on High Performance
Computing (HiPC), India (1999)
Program Co-Chair, International Conference on Parallel and
Distributed Systems (ICPDS), Taiwan (1998)
Program Co-Chair, 10th Workshop on Languages and Compilers for
Parallel
Computers (LCPC-10), Minneapolis, MN (1997)
Program Chair, International Conference on Supercomputing (ICS),
Philadelphia, PA (1996)
Program Vice-Chair, International Conference on Supercomputing
(ICS), Barcelona, Spain (1995)
General Co-Chair, International Symposium on Computer
Architecture (ISCA), Chicago, IL (1994)
Program Co-Chair, International Conference on Parallel
Processing (ICPP), St. Charles, IL (1990)
High-performance and low-power multi-core architectures,
compilation techniques that support multi-threading and speculation,
dynamic compilation, binary translation, parallel machine
organizations, and OS for multi-core embedded systems
Current Research Efforts
My main research effort is on the design of future generations of
high-performance and low-power computer systems, which include both
microprocessors and multiprocessors. I am interested in issues
related to their machine architectures, programming models,
compilation techniques and system software.
In the design of future generations of microprocessors,
we are focusing on multi-threaded, multi-core architectures
that exploit both thread-level and instruction-level parallelism
possibly with speculation support to achieve high performance with
reduced power consumption. The targeted systems span from
large-scale parallel machines to application-specific
embedded systems.
Our compiler effort is focused on a profile-based approach that
supports both medium-grained (loop iteration-level) and
fine-grained (instruction-level) parallelism with speculation,
low power and latency hiding schemes. Research is focused on
both static (at compile time) and dynamic (at runtime) compilation
techniques. We also focus on binary translation techniques that
support cross-platform execution. Another area of interests is
on new parallel programming models that support domain experts
for their specific applications.
System software research currently focuses on operating system
support for multi-core embedded systems, and on supporting
virtualization for various applications.
We use experimental approach to those design issues with on-going
development of compiler and architectural simulation infrastructure to
support our research effort.
The views and opinions expressed in this page are strictly those of the page author. The contents of this page have not been reviewed or approved by the University of Minnesota.
