Pen-Chung Yew

 

Professor

Department of Computer Science and Engineering

University of Minnesota at Twin Cities

4-192 Keller Hall

200 Union Street, SE

Minneapolis, MN 55455, USA

Contact: <yew> {at} cs [dot] umn [dot] edu

 

Education

Ph.D. 1981

   University of Illinois at Urbana-Champaign, Computer Science.

M.S. 1977

University of Massachusetts at Amherst, Computer Engineering

B.S. 1972

National Taiwan University, Electrical

 

 

PhD Theses Completed

University of Minnesota

 

25. Sanyam Mehta, Scalable Compiler Optimization for Improving the Memory System Performance in Multi- and Many-core Processors, October 2014.

24. Jagan Jayaraj, A Strategy for High Performance in Computational Fluid Dynamics, August 2013

23. Pei-Hung Lin, Performance Portability Strategies for Computational Fluid Dynamics (CFD) Applications on HPC Systems, Pei-Hung Lin, June. 2013

22. Tong Chen, Memory Profiling and Management, Tong Chen, December. 2010

21. Venkatesan Packirisamy Exploring Efficient Architecture Design for Thread-Level Speculation - Power and Performance Perspectives, March 2009

20. Jinpyo Kim, COBRA: A Framework for Profiling and Binary Re-Adaptation, January. 2008

19. Shengyue Wang, Compiler Techniques for Thread-Level Speculation, Feb. 2007

18. Xiaoru Dai, A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion, June 2005

17. Sangyuen Cho, A High-Bandwidth Memory Pipeline for Wide-Issue Processors, December 2002

16. Bixia Zheng, Integrating Scalar Analyses and Optimizations in a Parallelizing and Optimizing Compiler, February 2000

15. Jinseok Kong, Binding Time in Distributed Shared Memories, June 1999

 

 

University of Illinois at Urbana-Champaign

 

14. Hock Beng Lim, On the Integration of Compiler-Directed Cache Coherence and Data Prefetching, January, 1999

13. Jenn-Yuan Tsai, Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading, April, 1998

12. Lynn Choi, Hardware and Compiler Support for Cache Coherence in Large-Scale Shared-Memory Multiprocessors, April, 1996

11.Pavlos Konas, Parallel Architectural Simulations on Shared Memory Multiprocessors, August 1994.

10. David K. Poulsen, Memory Latency Reduction via Data Prefetching and Data Forwarding in Shared-Memory Multiprocessors, August 1994.

9. Ding-Kai Chen, Compiler Optimization for Parallel Loops with Fine-Grained Synchronization, May 1994

8. William Hsu, Multiprocessor Communication: Design and Technology, August 1992

7. Hong-Men Su, On Multiprocessor Synchronization and Data Transfer, January 1992.

6. David John Lilja, Processor Parallelism Considerations and Memory Latency Reduction in Shared Memory Multiprocessors, September 1991.

5. Timothy Alden Davis, A Parallel Algorithm for Sparse Unsymmetric LU Factorization, September 1989.

4. Zhiyuan Li, Intraprocedural and Interprocedural Data Dependence Analysis for Parallel Computing, August 1989.

3. Peiyi Tang, Self-Scheduling, Data Synchronization and Program Transformation for Multiprocessor Systems, January 1989.

2. Roland Lee, The Effectiveness of Caches and Data Prefetch Buffers in Large-Scale Shared Memory Multiprocessors, July 1987.

1. N.F. Tzeng, Fault-Tolerant Multiprocessor Interconnection Networks and Their Fault-Diagnoses, Aug. 1986