Pen-Chung Yew

 

Professor

Department of Computer Science and Engineering

University of Minnesota at Twin Cities

4-192 Keller Hall

200 Union Street, SE

Minneapolis, MN 55455, USA

Contact: <yew> {at} cs [dot] umn [dot] edu

Education

Ph.D. 1981

   University of Illinois at Urbana-Champaign, Computer Science.

M.S. 1977

†† University of Massachusetts at Amherst, Computer Engineering

B.S. 1972

†† National Taiwan University, Electrical Engineering

 

Current Research Interests

My research interests include computer architecture and compilers targeting future generations of high-performance and low-power multi- and many-core systems. Areas of focus include: system virtualization and dynamic binary translation, high-performance memory systems, parallel program debugging and testing, and parallel simulation techniques for many-core systems.

 

Recent Publications (Last 5 years, updated 3/1/2018)

Dynamic Binary Translation (DBT) and System Virtualization

 

      W. Wang, S. McCamant, A. Zhai, P.C. Yew, Enhancing DBT Performance Through Automatically Learned Translation Rules, 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2018

      W. Wang, J. Wu, T. Li, X. Gong, P.C. Yew, Improving Dynamically-Generated Code Performance on Dynamic Binary Translator, Proc. of 14th Int'l Conf. on Virtual Execution Environments (VEE), March 2018

      W. Wang, P.C. Yew, A. Zhai, S. McCamant, Y. Wu, J. Bobba, Enabling Cross-ISA Offloading for COTS Binaries, The 15th ACM International Conf. on Mobile, Systems, Applications, and Services (MobiSys), June 2017

      W. Wang, A. Zhai and P.C. Yew, A General Persistent Code Caching Framework for Dynamic Binary Translation, Proc. of the 2016 USENIX Annual Technical Conference (ATC), June 2016

      Y.H. Lu, D.Y. Hong, T.Y. Wu, J.J. Wu, P. Liu, W.C. Hsu, and P.C. Yew, DBILL: An Efficient and Retargetable Dynamic Binary Instrumentation Framework using LLVM Backend, Proc. of 10th Int'l Conf. on Virtual Execution Environments (VEE), March 2014

      C.R. Chang, J.J. Wu, P. Liu, W.C. Hsu, and P.C. Yew, Efficient Memory Virtualization for Cross-ISA System Mode Emulation, Proc. of 10th Int'l Conf. on Virtual Execution Environments (VEE), March 2014

       D.Y. Hong, J.J. Wu, P.C. Yew, W.C. Hsu, C.C. Hsu, P. Liu, C.M. Wang and Y.C. Chung, Efficient and Retargetable Dynamic Binary Translation on Multicores, IEEE Transactions on Parallel and Distributed Systems (TPDS), March 2014

       C.C. Hsu, J.J. Wu, P.C. Yew, D.Y. Hong, C.M. Wang, and W.C. Hsu, Improving Dynamic Binary Optimization Through Early-Exit Guided Code Region Formation, 9th Int'l Conf on Virtual Execution Environments (VEE), March 2013

 

Compiler Optimization

 

      S. Mehta and P.C. Yew, Variable Liberalization, ACM Transactions on Architecture and Code Optimization (TACO), Vol. 13, Issue 3, September 2016

       S. Mehta, R. Garg, N. Trivedi and P.C. Yew, TurboTiling: Leveraging Prefetching to Boost Performance of Tiled Codes, Proc. of the 2016 Int't Conf. on Supercomputing (ICS), June 2016.

      S. Mehta and P.C. Yew, Improving Compiler Scalability: Optimizing Programs at Small Price, Proc. of ACM SIGPLAN Intíl Conf. on Programming Languages Design and Implementation (PLDI), June 2015

      S. Mehta, Z. Fang, A. Zhai and P.C. Yew, Multistage Coordinated Prefetching for Present-Day Processors, Proc. of the 2014 Int't Conf. on Supercomputing (ICS), June 2014

      S. Mehta, P.H. Lin, and P.C. Yew, Revisiting Loop Fusion in the Polyhedral Framework, Proc. of ACM SIGPLAN 19th Annual Symp. on Principles and Practice of Parallel Programming (Ppopp), February 2014

       S. Mehta, G. Beeraka and P.C. Yew, Tile Size Selection Revisited, ACM Transactions on Architecture and Code Optimization (TACO), Vol. 10, No. 4, 2013

      L. Gao, L. Li, J.L. Xue and P.C. Yew, SEED: A Statically-Greedy and Dynamically-Adaptive Approach for Speculative Loop Execution, IEEE Transaction on Computers (TC), Vol. 62, No. 5, May 2013

 

Parallel Program Debugging and Testing

 

      C. Wu, Z. Wang, X. Yuan, Z. Wang, L. Li, P. C. Yew, J. Huang, X. Feng, Y. Lan, Y. Chen, Y. Lai, Y. Guan, Using Local Clocks to Reproduce Concurrency Bugs, IEEE Trans. on Software Engineering (TSE), to appear in 2018.

      L. Zhong, W. Hou, X. Feng, Z. Zhang, P.C. Yew, RARE: An Efficient Static Fault Detection Framework for Definition-Use Faults in Large Programs, IEEE Access, to appear in 2018

      X. Yuan, C. Wu, Z. Wang, J. Li, X. Feng, P.C. Yew, Y. Lan, Y. Chen, J. Huang, Y. Guan, Reproducing Concurrency Bugs using Local Clocks, Proc. of Int'l Conf. on Software Engineering (ICSE), May, 2015

      W. Wang, C. Wu, P.C. Yew, X. Shen, X. Yuan, Z. Wang, J. Li, X. Feng, Concurrency Bugs Localization Using Shared Memory Access Pairs, 29th IEEE/ACM International Conference on Automated Software Engineering (ASE), September 2014

      X. Yuan, C. Wu, P.C. Yew, W. Wang, Z. Wang, J. Li and D. Xu, Synchronization Identification through On-the-Fly Test, Proc. of 2013 Euro-Par Conference (Euro-Par), August 2013

 

Computer Architectures

 

      W. Zhang, X., Ji, Y. Lu, H. Wang, H. Chen, P.C. Yew, Prophet: A Parallel Instruction-Oriented Many-Core Simulator, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 28, Issue 10, October 2017.

      W. Zhang, X. Ji, S. Yu, H. Chen, T. Li and P.C. Yew, VarCatcher: A Framework for Tackling Performance Variability of Parallel Workloads on Multicores, IEEE Transactions on Parallel and Distributed Systems (TPDS), April 2017

       Z. Fang, S. Mehta, P.C. Yew, A. Zhai, J. Greensky, G. Beeraka, B. Zang, Measuring Micro-architectural Details of Multi- and Many-core Memory Systems Through Micro-benchmarking, ACM Transactions on Architecture and Code Optimization (TACO), Vol.11, Issue 4, January 2015.

      F. Lv, L. Liu, M.H. Cui, L. Wang, Y. Liu, X. Feng, P.C. Yew, WiseThrottling: A New Asynchronous Task Scheduler for Mitigating I/O Bottleneck in Large-Scale Datacenter Servers, J. of Supercomputing, 2015

      C.J. Chang, Y.C. Peng, C.C. Chen, T.F. Chen and P.C. Yew, Adaptive Granularity and Coordinated Management for Timely Prefetching in Multi-core Systems, 2015 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), May 28 2015

      A. Holey, V. Mekkat, P.C. Yew, A. Zhai, Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor, ACM Transactions on Architecture and Code Optimization (TACO), Vol 12, Issue 1, March 2015.

      C. Wu, J. Li, D. Xu, P.C. Yew, J. Li, and Z. Wang, FPS: A Fair-progress Process Scheduling Policy on Shared-Memory Multiprocessors, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 26, No. 2, February 2015, pp. 444-454

      F. Lv, H.M. Cui, L. Wang, L. Liu, C.G. Wu, X.B. Feng and P.C. Yew, Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platform, J. of Computer Science and Technology (JCSE), 29(1): 21-37, 2014

      C.F. Chen, C.C. Chen, et al, DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation, Proc. of 51th International Design Automation Conference (DAC), June 2014

      S.H. Chen, S.M. Lin, K.Y. Chen, Y.H. Chang, P.C. Yew, C.C. Ho, A Systematic Methodology for OS Benchmarks Characterization, Proc. of ACM Intíl Conf. on Reliable and Convergent Systems (RACS), October 2013

      V. Mekkat, A. Holey, P.C. Yew and A. Zhai, Managing Last-Level Cache in a Heterogeneous Multicore Processor, Proc. of Int'l Conf. on Parallel Architectures and Compiler Techniques (PACT), September 2013.

 

Complete Publication List (UMN Experts Page)

Professional Activities

PhD Students