Hardware-level and timing attacks and defenses

Cynthia Sturton, Matthew Hicks, David Wagner, and Samuel T. King. “Defeating UCI: Building stealthy and malicious hardware”. In IEEE Symposium on Security and Privacy “Oakland”, pages 64–77, Oakland, CA, USA, May 2011.
[IEEE]

David Molnar, Matt Piotrowski, David Schultz, and David Wagner. “The program counter security model: Automatic detection and removal of control-flow side channel attacks”. In International Conference on Information Security and Cryptology (ICISC), pages 156–168, Seoul, Korea, December 2005.
[Springer]

Question: The Molnar et al. paper mentions that its PC-trace side channel model doesn't include any attacks based on the same instruction taking a different amount of time to execute in different circumstances. This means that the paper's transformation doesn't protect against timing attacks where timing depends on data being present or not present in a cache, which can be quite dangerous (the optional paper is about these, for instance). Following Molnar et al.'s suggestion of a hardware/software contract, sketch out how you might modify a CPU architecture so that code could be compiled without cache-timing side channels.

Optional

Boris Köpf, Laurent Mauborgne, and Martín Ochoa. “Automatic quantification of cache side-channels.” In Computer Aided Verification (CAV), pages 564–580, Berkeley, CA, USA, July 2012.
[Springer]