University of Minnesota
Machine Architecture and Organization
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Class Schedule

Week

Date

Topics

Readings

Labs

Assignments

1 01/21 Introduction I 1.1-1.10   Lab 0 (Emery Mizero)
01/23 Data Representation I 2.1    
2 01/26 Data Representation II 2.2 Lab I: Data Lab (Ran Hu) Lab 0 Due (11:55PM)
01/28 Data Representation III 2.3    
01/30 Data Representation IV 2.4-2.5    
3 02/02 Data Representation V     Assignment I (Albert Jonathan and Ran Hu)
02/04 Machine-Level Code I 3.1-3.3    
02/06 Machine-Level Code II 3.4-3.5 Lab I due  
4 02/09 Machine-Level Code III 3.6   Assignment I Due
02/11 Machine-Level Code IV 3.7 Lab II: Bomb Lab (Emery Mizero)  
02/13 Machine-Level Code V 3.8    
5 02/16 Machine-Level Code VI 3.9    
02/18 Machine-Level Code VII 3.10-3.12    
02/20 Machine-Level Code VIII 3.13-3.15   Assignment II (Hanlin Zhu and Emery Mizero)
6 02/23 Machine-Level Code IX 8.1, 8.6 Lab II due  
02/25 Architecture I 4.1    
02/27

Review

  Lab III: Buffer Lab (Kartik Ramkrishnan) Assignment II Due
7 03/02

Quiz

     
03/04 Architecture II 4.2    
03/06 Architecture III 4.3    
8 03/09 Architecture IV 4.4    
03/11 Architecture V 4.5-4.6 Lab III due Assignment III (Kyle Winkelman and Emery Mizero)
03/13 Optimization I 5.1-5.8    
Spring Break
9 03/23 Optimization II 5.9-5.15 Lab IV: Architecture Lab (Albert Jonathan) Assignment III (original due date)
03/25 Memory Hierachy I 6.1-6.3   Assignment III Due (extended)
03/27 Memory Hierarchy II 6.4    
10 03/30 Memory Hierarchy III    
04/01 Memory Hierarchy IV 6.5-6.7   Assignment IV (Albert Jonathan and Nishad Trivedi)
04/03 Memory Hierarchy V 9.1-9.3 Lab IV Due  
11 04/06 Memory Hierarchy VI 9.4-9.6    
04/08 Memory Hierarchy VII 9.7 Lab V: Cache Lab (Ravi Raj)  
04/10 Memory Hierarchy VIII 9.9    
12 04/13 Memory Hierarchy IX 9.10-9.12   Assignment IV Due
04/15

Review

     
04/17

Quiz

     
13 04/20 Linking I 7.1-7.7    
04/22 Linking II 7.8-7.14    
04/24 Logic Design I AACv4 3, 7    
14 04/27 Logic Design II AACv4 8 Lab V Due  
04/29 Logic Design III AACv4 9   Assignment V (Ravi Raj and Kartik Ramkrishnan)
05/01 Logic Design IV AACv4 10    
15 05/04 Logic Design V AACv4 11    
05/06

Final Review

     
05/08

Final Review

    Assignment V Due
  05/12 Final exam (12:20 lecture), 1:30-3:30pm, 101 Fraser (same location as lectures)  
  05/14 Final exam (3:35 lecture), 8:00am-10:00am, 133 Tate Physics (same location as lectures)